1. Field of the Invention
This invention relates to junction field effect transistors and more particularly to a modified architecture and method of manufacture thereof.
2. Description of Related Art
A junction field-effect transistor (JFET) is unipolar device with a source electrode, a drain electrode, and at least one gate electrode which uses the depletion region of one or more reverse-biased P-N junctions to modulate the cross-sectional area available for current flow. The current is due to carriers of one polarity only. A JFET consists of a conductive channel with two ohmic contacts, one acting as the source and the other as the drain. When a positive voltage is applied to the drain with respect to the source, electrons flow from the source to the drain. The third electrode, the gate electrode(s), form(s) a rectifying junction with the channel.
FIG. 3 shows a prior art surface gate JFET with semiconductor substrate with an N doped active region A formed above an N+ drain region D. In the substrate are formed N+ gate regions G1 and G2 near the sides of source region S. Above the gate regions G1 and G2 are formed gate electrodes Tg1 and Tg2. Above the periphery of the gate regions G1 and G2 is formed an oxide dielectric layer OX with an opening therethrough with a source electrode Ts extending down to contact the source region S of the JFET. A problem is that source region S is formed between and narrowly separated from the gate regions G1 and G2. Dielectric layer OX isolates the source electrode Ts from the gate regions G1 and G2 and gate electrodes Tg1 and Tg2.
To fabricate a prior art surface gate JFET of the kind seen in FIG. 3, two critical lithography steps are required. The source region S must be aligned between the diffused gate regions G1 and G2 and the contact windows must be aligned to the diffused regions S, Gi, and G2. Any misalignment can result in an electrical short circuit between a gate and a source. Such a design requires employing a critical alignment and manufacturing process for the purpose of staying within the desired margin of error and in order to reach a sufficiently high yield with the current state of the art. There is a need for a process with far less critical dimensional constraints.